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DATA SHEET
MOS INTEGRATED CIRCUIT
PD431000A-X
1 M-BIT CMOS STATIC RAM 128 K-WORD BY 8-BIT EXTENDED TEMPERATURE OPERATION
Description
The PD431000A-X is a high speed, low power, and 1,048,576 bits (131,072 words by 8 bits) CMOS static RAM. The PD431000A-X has two chip enable pins (CE1, CE2) to extend the capacity. A and B versions are wide voltage versions. The PD431000A-X are packed in 32-pin plastic TSOP(I).
Features
* 131,072 words by 8 bits organization * Fast access time: 85, 100, 120, 150 ns (MAX.) * Wide voltage operation (A version: VCC = 3.0 V to 5.5 V, B version: VCC = 2.7 V to 5.5 V) * Operating ambient temperature: TA = -25 to + 85 C * Output Enable input for easy application * Two Chip Enable inputs: CE1, CE2
Part number
Access time ns (MAX.)
Operating supply voltage V 4.5 to 5.5 3.0 to 5.5 2.7 to 5.5
Operating ambient temperature C -25 to +85
Supply current At operating mA (MAX.) 70 35 Note 2 30 Note 3 At standby A (MAX.) 50 26 Note 4 22 Note 5
PD431000A-X PD431000A-AX PD431000A-BX
70, 85, 100 70 Note 1 , 100, 120 70 Note 1 , 100, 120, 150
Notes 1. 2. 3. 4.
VCC = 4.5 to 5.5 V 70 mA (VCC > 3.6 V) 70 mA (VCC > 3.3 V) 50 A (VCC > 3.6 V)
5. 50 A (VCC > 3.3 V)
The information in this document is subject to change without notice. Document No. M10430EJ4V0DS00 (4th edition) Date Published December 1997 N CP(K) Printed in Japan
The mark
shows major revised points.
(c)
1995
PD431000A-X
Ordering Information
Access time ns (MAX.) 70 85 100 100 120 100 120 150 32-pin Pastic TSOP(I) (8 x 20 mm) (Reverse bent) 70 85 100 100 120 100 120 150 32-pin Plastic TSOP(I) (8 x 13.4 mm) (Normal bent) 70 85 100 100 120 100 120 150 32-pin Plastic TSOP(I) (8 x 13.4 mm) (Reverse bent) 70 85 100 100 120 100 120 150 2.7 to 5.5 B Version 3.0 to 5.5 A Version 4.5 to 5.5 -- 2.7 to 5.5 B Version 3.0 to 5.5 A Version 4.5 to 5.5 -- 2.7 to 5.5 B Version 3.0 to 5.5 A Version 4.5 to 5.5 -- 2.7 to 5.5 B Version 3.0 to 5.5 A Version Operating supply voltage V 4.5 to 5.5 Operating temperature C -25 to +85
Part number
Package
Remark
PD431000AGZ-70X-KJH PD431000AGZ-85X-KJH PD431000AGZ-10X-KJH PD431000AGZ-A10X-KJH PD431000AGZ-A12X-KJH PD431000AGZ-B10X-KJH PD431000AGZ-B12X-KJH PD431000AGZ-B15X-KJH PD431000AGZ-70X-KKH PD431000AGZ-85X-KKH PD431000AGZ-10X-KKH PD431000AGZ-A10X-KKH PD431000AGZ-A12X-KKH PD431000AGZ-B10X-KKH PD431000AGZ-B12X-KKH PD431000AGZ-B15X-KKH PD431000AGU-70X-9JH PD431000AGU-85X-9JH PD431000AGU-10X-9JH PD431000AGU-A10X-9JH PD431000AGU-A12X-9JH PD431000AGU-B10X-9JH PD431000AGU-B12X-9JH PD431000AGU-B15X-9JH PD431000AGU-70X-9KH PD431000AGU-85X-9KH PD431000AGU-10X-9KH PD431000AGU-A10X-9KH PD431000AGU-A12X-9KH PD431000AGU-B10X-9KH PD431000AGU-B12X-9KH PD431000AGU-B15X-9KH
32-pin Plastic TSOP(I) (8 x 20 mm) (Normal bent)
--
2
PD431000A-X
Pin Configuration (Marking side)
32-pin plastic TSOP (I) (8 x 20mm) (Normal bent)
[ PD431000AGZ-X-KJH]
A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE1 I/O8 I/O7 I/O6 I/O5 I/O4 GND I/O3 I/O2 I/O1 A0 A1 A2 A3
32-pin plastic TSOP (I) (8 x 20mm) (Reverse bent)
[ PD431000AGZ-X-KKH]
OE A10 CE1 I/O8 I/O7 I/O6 I/O5 I/O4 GND I/O3 I/O2 I/O1 A0 A1 A2 A3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4
A0 to A16 : I/O1 to I/O8 : CE1, CE2 : WE : OE : VCC : GND : NC :
Address inputs Data inputs/outputs Chip Enable 1, 2 Write Enable Output Enable Power supply Ground No connection
3
PD431000A-X
32-pin plastic TSOP (I) (8 x 13.4mm) (Normal bent)
[ PD431000AGU-X-9JH]
A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
OE A10 CE1 I/O8 I/O7 I/O6 I/O5 I/O4 GND I/O3 I/O2 I/O1 A0 A1 A2 A3
32-pin plastic TSOP (I) (8 x 13.4mm) (Reverse bent)
[ PD431000AGU-X-9KH]
OE A10 CE1 I/O8 I/O7 I/O6 I/O5 I/O4 GND I/O3 I/O2 I/O1 A0 A1 A2 A3
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4
A0 to A16 : I/O1 to I/O8 : CE1, CE2 : WE : OE : VCC : GND NC
Address inputs Data inputs/outputs Chip Enable 1, 2 Write Enable Output Enable Power supply : Ground : No connection
4
PD431000A-X
Block Diagram
VCC GND
A0 A16 Address buffer Row decoder Memory cell array 1,048,576 bits
I/O1 Input data controller I/O8
Sense/Switch Column decoder
Output data controller
Address buffer
CE1
CE2
OE
WE
Truth Table
CE1 H x L L L CE2 x L H H H OE x x H L x WE x x H H L Output disable Read Write DOUT DIN Mode Not selected I/O High impedance ICCA Supply current ISB
Remark x : Don't care
5
PD431000A-X
Electrical Characteristics Absolute Maximum Ratings
Parameter Supply voltage Input/Output voltage Operating ambient temperature Storage temperature Symbol VCC VT TA Tstg Rating -0.5 Note to +7.0 -0.5 Note to VCC + 0.5 -25 to +85 -55 to +125 Unit V V C C
Note -3.0 V (MIN.) (Pulse width 30 ns) Caution Exposing the device to stress above those listed in absolute maximum ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational sections of this characteristics. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Recommended Operating Conditions
PD431000A-X
Parameter Supply voltage High level input voltage Low level input voltage Operating ambient temperature Symbol VCC VIH VIL TA MIN. 4.5 2.4 -0.3 Note -25 MAX. 5.5 VCC + 0.5 +0.6 +85
PD431000A-AX
MIN. 3.0 2.4 -0.3 Note -25 MAX. 5.5 VCC +0.5 +0.5 +85
PD431000A-BX
MIN. 2.7 2.4 -0.3 Note -25 MAX. 5.5 VCC + 0.5 +0.5 +85 Unit V V V C
Note -3.0 V (MIN.) (Pulse width 30 ns)
6
PD431000A-X
DC Characteristics (Recommended operating conditions unless otherwise noted)
PD431000A-X PD431000A-AX PD431000A-BX
MIN. TYP. MAX. MIN. TYP. MAX. MIN. TYP. MAX. Input leakage current I/O leakage current ILI ILO VIN = 0 V to VCC VI/O = 0 V to VCC, CE1 = VIH or CE2 = VIL or WE = VIL or OE = VIH CE1 = VIL, CE2 = VIH Minimum cycle time II/O = 0 mA -1.0 -1.0 +1.0 -1.0 +1.0 -1.0 +1.0 -1.0 +1.0 -1.0 +1.0 A +1.0 A
Parameter
Symbol
Test Conditions
Unit
Operating supply ICCA1 current
40 VCC 3.6 V VCC 3.3 V --
70 -- -- 15
40 15
70 35 -- 15 10 -- 10
40 -- 15
70 -- 30 15 -- 8 10
mA
ICCA2
CE1 = VIL, CE2 = VIH, II/O = 0 mA
VCC 3.6 V VCC 3.3 V
-- -- 10
ICCA3
CE1 0.2 V, CE2 VCC - 0.2 V, Cycle = 1 MHz, II/O = 0 mA, VIL 0.2 V, VIH VCC - 0.2 V VCC 3.6 V VCC 3.3 V
-- -- 3
8 -- 3 2 -- -- 0.5 -- -- 0.5 -- 2.4 2.4 50 26 -- 50 26 -- 2.4 2.4 0.4 0.4 -- -- 0.5 -- -- 0.5
-- 7 3 -- 2 50 -- 22 50 -- 22 V mA
Standby supply current
ISB
CE1 = VIH or CE2 = VIL VCC 3.6 V VCC 3.3 V
-- -- 1 50 -- -- 1 50 -- --
ISB1
CE1 VCC - 0.2 V, CE2 VCC - 0.2 V VCC 3.6 V VCC 3.3 V
A
--
ISB2
CE2 0.2 V VCC 3.6 V VCC 3.3 V
-- -- 2.4 --
High level output voltage Low level output voltage
VOH
IOH = -1.0 mA, VCC 4.5 V IOH = -0.5 mA
VOL
IOL = 2.1 mA, VCC 4.5 V IOL = 1.0 mA
0.4 --
0.4 0.4
V
Remark These DC characteristics are in common regardless of package types and access time.
Capacitance (TA = 25 C, f = 1 MHz)
Parameter Input capacitance Input/Output capacitance Symbol CIN CI/O VIN = 0 V VI/O = 0 V Test conditions MIN. TYP. MAX. 6 10 Unit pF pF
Remarks 1. VIN: Input voltage 2. These parameters are periodically sampled and not 100 % tested.
7
PD431000A-X
AC Characteristics (Recommended operating conditions unless otherwise noted)
AC Test Conditions Input waveform (Rise/fall time 5 ns) Input pulse levels 0.6 V to 2.4 V: PD431000A-X 0.5 V to 2.4 V: PD431000A-AX
PD431000A-BX
1.5 V
Test points
1.5 V
Output waveform
1.5 V
Test points
1.5 V
Output load AC characteristics should be measured with the following output load conditions.
Output load conditions Part number tAA, tCO1, tCO2, tOE, tOH tLZ1, tLZ2, tOLZ, tHZ1, tHZ2, tOHZ, tWHZ, tOW 1TTL + 5 pF
PD431000A-A10X, 431000A-A12X PD431000A-B10X, 431000A-B12X PD431000A-B15X PD431000A-X
1TTL + 50 pF
1TTL + 100 pF See Figure 1
1TTL + 5 pF See Figure 2
Figure 1
+5 V
Figure 2
+5 V
1.8 k
1.8 k
I/O (Output)
I/O (Output)
990
100 pF CL
990
5 pF CL
Remark
CL includes capacitances of the probe and jig, and stray capacitances.
8
PD431000A-X
Read Cycle (1/2)
VCC 4.5 V VCC 3.0 V
Parameter
PD431000A-70X Symbol PD431000A-AX PD431000A-85X PD431000A-10X PD431000A-A10X PD431000A-BX
MIN. MAX. MIN. 85 70 70 70 35 10 10 10 5 25 25 25 10 10 10 5 30 30 30 85 85 85 45 10 10 10 5 35 35 35 MAX. MIN. 100 100 100 100 50 10 10 10 5 35 35 35 MAX. MIN. 100 100 100 100 50 MAX.
Unit
Condition
Read cycle time Address access time CE1 access time CE2 access time OE to output valid Output hold from address change CE1 to output in low impedance CE2 to output in low impedance OE to output in low impedance CE1 to output in high impedance CE2 to output in high impedance OE to output in high impedance
tRC tAA tCO1 tCO2 tOE tOH tLZ1 tLZ2 tOLZ tHZ1 tHZ2 tOHZ
70
ns ns ns ns ns ns ns ns ns ns ns ns Note
Note
See the output load.
Remark These AC characteristics are in common regardless of package types.
Read Cycle (2/2)
VCC 3.0 V Parameter VCC 2.7 V Unit Condition
Symbol PD431000A-A12X PD431000A-B10X PD431000A-B12X PD431000A-B15X MIN. MAX. MIN. 100 120 120 120 60 10 10 10 5 40 40 40 10 10 10 5 35 35 35 100 100 100 50 10 10 10 5 40 40 40 MAX. MIN. 120 120 120 120 60 10 10 10 5 50 50 50 MAX. MIN. 150 150 150 150 70 MAX.
Read cycle time Address access time CE1 access time CE2 access time OE to output valid Output hold from address change CE1 to output in low impedance CE2 to output in low impedance OE to output in low impedance CE1 to output in high impedance CE2 to output in high impedance OE to output in high impedance
tRC tAA tCO1 tCO2 tOE tOH tLZ1 tLZ2 tOLZ tHZ1 tHZ2 tOHZ
120
ns ns ns ns ns ns ns ns ns ns ns ns Note
Note
See the output load.
Remark These AC Characteristics are in common regardless of package types.
9
PD431000A-X
Read Cycle Timing Chart
tRC
Address (Input) tAA CE1 (Input) tCO1 tLZ1 tHZ1 tOH
CE2 (Input)
tCO2 tLZ2 tHZ2
OE (Input) tOE tOLZ I/O (Output) High impedance Data out tOHZ
Remark In read cycle, WE should be fixed to high level.
10
PD431000A-X
Write Cycle (1/2)
VCC 4.5 V VCC 3.0 V
Parameter
PD431000A-70X Symbol PD431000A-AX PD431000A-85X PD431000A-10X PD431000A-A10X PD431000A-BX
MIN. MAX. MIN. 85 70 70 70 0 60 5 35 0 25 5 5 30 5 MAX. MIN. 100 80 80 80 0 60 0 60 0 35 5 MAX. MIN. 100 80 80 80 0 60 0 60 0 35 MAX.
Unit
Condition
Write cycle time CE1 to end of write CE2 to end of write Address valid to end of write Address setup time Write pulse width Write recovery time Data valid to end of write Data hold time WE to output in high impedance Output active from end of write
tWC tCW1 tCW2 tAW tAS tWP tWR tDW tDH tWHZ tOW
70 55 55 55 0 50 5 35 0
ns ns ns ns ns ns ns ns ns ns ns Note
Note See the output load. Remark These AC characteristics are in common regardless of package types. Write Cycle (2/2)
VCC 3.0 V Parameter VCC 2.7 V Unit Condition
Symbol PD431000A-A12X PD431000A-B10X PD431000A-B12X PD431000A-B15X MIN. MAX. MIN. 100 80 80 80 0 60 0 60 0 40 5 5 35 5 MAX. MIN. 120 100 100 100 0 85 0 60 0 40 5 MAX. MIN. 150 120 120 120 0 100 0 80 0 50 MAX.
Write cycle time CE1 to end of write CE2 to end of write Address valid to end of write Address setup time Write pulse width Write recovery time Data valid to end of write Data hold time WE to output in high impedance Output active from end of write
tWC tCW1 tCW2 tAW tAS tWP tWR tDW tDH tWHZ tOW
120 100 100 100 0 85 0 60 0
ns ns ns ns ns ns ns ns ns ns ns Note
Note See the output load. Remark These AC Characteristics are in common regardless of package types.
11
PD431000A-X
Write Cycle Timing Chart 1 (WE Controlled)
tWC Address(Input) tCW1 CE1 (Input) tCW2 CE2 (Input) tAW tAS WE (Input) tOW tWHZ I/O (Input/Output) Indefinite data out High impedance tDW Data in tDH High impedance Indefinite data out tWP tWR
Cautions 1. During address transition, at least one of pins CE1, CE2, WE should be inactivated. 2. When I/O pins are in the output state, do not apply to the I/O pins signals that are opposite in phase with output signals. Remarks 1. Write operation is done during the overlap time of a low level CE1, WE, and a high level CE2. 2. If CE1 changes to low level at the same time or after the change of WE to low level, or if CE2 changes to high level at the same time or after the change of WE to low level, the I/O pins will remain high impedance state. 3. When WE is at low level, the I/O pins are always high impedance. When WE is at high level, read operation is executed. Therefore OE should be at high level to make the I/O pins high impedance.
12
PD431000A-X
Write Cycle Timing Chart 2 (CE1 Controlled)
tWC Address (Input)
tAS CE1 (Input) tCW2 CE2 (Input) tAW tWP WE (Input)
tCW1
tWR
tDW High impedance I/O (Input) Data in
tDH High impedance
Cautions 1. During address transition, at least one of pins CE1, CE2, WE should be inactivated. 2. When I/O pins are in the output state, do not apply to the I/O pins signals that are opposite in phase with output signals. Remark Write operation is done during the overlap time of a low level CE1, WE, and a high level CE2.
13
PD431000A-X
Write Cycle Timing Chart 3 (CE2 Controlled)
tWC Address (Input)
tCW1 CE1 (Input)
tAS CE2 (Input) tAW tWP WE (Input)
tCW2
tWR
tDW High impedance I/O (Input) Data in
tDH High impedance
Cautions 1. During address transition, at least one of pins CE1, CE2, WE should be inactivated. 2. When I/O pins are in the output state, do not apply to the I/O pins signals that are opposite in phase with output signals. Remark Write operation is done during the overlap time of a low level CE1, WE, and a high level CE2.
14
PD431000A-X
Low VCC Data Retention Characteristics All Version (PD431000A-X, 431000A-AX, 431000A-BX: TA = -25 to +85 C)
Parameter Data retention supply voltage Symbol VCCDR1 VCCDR2 Data retention supply current ICCDR1 Test conditions CE1 VCC - 0.2 V, CE2 VCC - 0.2 V CE2 0.2 V VCC = 3.0 V, CE1 VCC - 0.2 V, CE2 VCC - 0.2 V or CE2 0.2 V VCC = 3.0 V, CE2 0.2 V 0 MIN. 2.0 2.0 0.5 TYP. MAX. 5.5 5.5 20Note 20Note ns Unit V
A
ICCDR2 Chip deselection to data retention mode Operation recovery time tCDR
0.5
tR
5
ms
Note 2.5 A (TA 40 C)
15
PD431000A-X
Data Retention Timing Chart (1) CE1 Controlled
tCDR 5.0 V 4.5 V
Note
Data retention mode
tR
VCC
CE1 VIH (MIN. ) VCCDR (MIN. ) CE1 VCC - 0.2 V
VIL (MAX. )
GND
Note
A version: 3.0 V, B version: 2.7 V
Remark On the data retention mode by controlling CE1, the input level of CE2 must be CE2 VCC - 0.2 V or CE2 0.2 V. The other pins (Address, I/O, WE, OE) can be in high impedance state. (2) CE2 Controlled
tCDR 5.0 V 4.5 V
Note
Data retention mode
tR
VCC
VIH (MIN. ) VCCDR (MIN. ) CE2
VIL (MAX. ) CE2 0.2 V GND
Note
A version: 3.0 V, B version: 2.7 V
Remark The other pins (CE1, Address, I/O, WE, OE) can be in high impedance state.
16
PD431000A-X
Package Drawings Notice of change in 32-pin plastic TSOP (I) (8 x 20 mm) standoff height We are changing the 32-pin plastic TSOP (I) (8 x 20 mm) standoff height 0.05 0.05 mm (low standoff height) to 0.1 0.05 mm (high standoff height). Each lot version is identified by the fifth character of the lot number. Difference between high standoff height and low standoff height Detail of lead end
Normal bent
Reverse bent
Q Q
High standoff height: Q = 0.1 0.05 mm Low standoff height: Q = 0.05 0.05 mm
Identification of each lot version Each lot version is identified by the fifth character of the lot number.
Fifth character of the lot number R H Lot version R version H version Standoff height 0.1 0.05 mm (High standoff height) 0.05 0.05 mm (Low standoff height)
Marking Example
JAPAN
D431000A-X
XXXX
XXXX
Lot number
17
PD431000A-X
High standoff height
32 PIN PLASTIC TSOP (I) (8x20)
detail of lead end 1 32 F G R
Q 16 17 E P I J A
L S
S C K
NOTES 1. Controlling dimension Millimeter. 2. Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition. 3. "A" excludes mold flash. (Includes mold flash : 8.3 mm MAX. <0.327 inch MAX.>)
B
N
S
D
ITEM A B C D E F G I J K L M N P Q R S
MM
MILLIMETERS 8.00.1 0.45 MAX. 0.5 (T.P.) 0.220.05 0.10.05 1.2 MAX. 0.970.08 18.40.1 0.80.2 0.1450.05 0.5 0.10 0.10 20.00.2 3 +5 -3 0.25 0.600.15 INCHES 0.3150.004 0.018 MAX. 0.020 (T.P.) 0.009 +0.002 -0.003 0.0040.002 0.048 MAX. 0.038 +0.004 -0.003 +0.005 0.724 -0.004 +0.009 0.031 -0.008 0.006 +0.002 -0.003 0.020 0.004 0.004 +0.009 0.787 -0.008 3 +5 -3 0.010 +0.006 0.024 -0.007 S32GZ-50-KJH1
18
PD431000A-X
High standoff height
32 PIN PLASTIC TSOP (I) (8x20)
detail of lead end 1 32 E S Q L
R 16 17 F K N S D MM C S B G
I P
NOTES 1. Controlling dimension
J
A
ITEM
MILLIMETERS 8.00.1 0.45 MAX. 0.5 (T.P.) 0.220.05 0.10.05 1.2 MAX. 0.970.08 18.40.1 0.80.2 0.1450.05 0.5 0.10 0.10 20.00.2 3 +5 -3 0.25 0.600.15
INCHES 0.3150.004 0.018 MAX. 0.020 (T.P.) 0.009 +0.002 -0.003 0.0040.002 0.048 MAX. 0.038 +0.004 -0.003 +0.005 0.724 -0.004 +0.009 0.031 -0.008 0.006 +0.002 -0.003 0.020 0.004 0.004 +0.009 0.787 -0.008 3 +5 -3 0.010 +0.006 0.024 -0.007 S32GZ-50-KKH1
Millimeter.
A B C D E F G I J K L M N P Q R S
2. Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition. 3. "A" excludes mold flash. (Includes mold flash : 8.3 mm MAX. <0.327 inch MAX.>).
19
PD431000A-X
Low standoff height
32 PIN PLASTIC TSOP (I) (8x20)
1
32
detail of lead end
S
Q 16 17
R
P I J A G
H L K
NOTES (1) Each lead centerline is located within 0.08 mm (0.003 inch) of its true position (T.P.) at maximum material condition. (2) "A" excIudes mold flash. (Includes mold flash : 8.3 mm MAX. < 0.327 inch MAX.>)
C D M
M
B
N
ITEM A B C D G H I J K L M N P Q R S
MILLIMETERS 8.00.1 0.45 MAX. 0.5 (T.P.) 0.200.10 1.02 MAX. 19.00.2 18.40.2 0.80.2 0.125 +0.10 -0.05 0.50.1 0.08 0.10 20.00.2 0.050.05 55 1.1 MAX.
INCHES 0.3150.004 0.018 MAX. 0.020 (T.P.) 0.0080.004 0.041 MAX. 0.7480.008 0.724 +0.009 -0.008 0.031 +0.009 -0.008 0.005 +0.004 -0.002 0.020 +0.004 -0.005 0.003 0.004 0.787 +0.009 -0.008 0.0020.002 55 0.044 MAX. S32GZ-50-KJH-3
20
PD431000A-X
Low standoff height
32 PIN PLASTIC TSOP (I) (8x20)
1
32
detail of lead end Q S R
16
17
K H
N L
D
M
M
C
B
G I P J A
NOTES (1) Each lead centerline is located within 0.08 mm (0.003 inch) of its true position (T.P.) at maximum material condition. (2) "A" excIudes mold flash. (Includes mold flash : 8.3 mm MAX. < 0.327 inch MAX.>)
ITEM A B C D G H I J K L M N P Q R S
MILLIMETERS 8.00.1 0.45 MAX. 0.5 (T.P.) 0.200.10 1.02 MAX. 19.00.2 18.40.2 0.80.2 0.125 +0.10 -0.05 0.50.1 0.08 0.10 20.00.2 0.050.05 55 1.1 MAX.
INCHES 0.3150.004 0.018 MAX. 0.020 (T.P.) 0.0080.004 0.041 MAX. 0.7480.008 0.724 +0.009 -0.008 0.031 +0.009 -0.008 0.005 +0.004 -0.002 0.020 +0.004 -0.005 0.003 0.004 0.787 +0.009 -0.008 0.0020.002 55 0.044 MAX. S32GZ-50-KKH-3
21
PD431000A-X
32PIN PLASTIC TSOP ( I ) (8x13.4)
detail of lead end 1 32 S
T
R L 16 17 Q P I J A G U
H K N D M
C
M
B
NOTE (1) Each lead centerline is located within 0.08 mm (0.003 inch) of its true position (T.P.) at maximum material condition. (2) "A" excludes mold flash. (Includes mold flash : 8.3 mm MAX. <0.331 inch MAX.>)
ITEM A B C D G H I J K L M N P Q R S T U
MILLIMETERS 8.00.1 0.45 MAX. 0.5 (T.P.) 0.220.05 1.00.05 12.40.2 11.80.1 0.80.2 0.145 +0.025 -0.015 0.5 0.08 0.08 13.40.2 0.10.05 3 +5 -3 1.2 MAX. 0.25 0.160.15
INCHES 0.3150.004 0.018 MAX. 0.02 (T.P.) 0.009 +0.002 -0.003 0.039 +0.003 -0.009 0.4880.008 0.465 +0.004 -0.005 0.031 +0.009 -0.008 0.0060.001 0.020 0.003 0.003 0.528 +0.008 -0.009 0.0040.002 3 +5 -3 0.048 MAX. 0.01 0.006 +0.007 -0.006 P32GU-50-9JH
22
PD431000A-X
32PIN PLASTIC TSOP ( I ) (8x13.4)
detail of lead end 1 32 Q R U L
T
16
17
S
K H
N
D
M
M
C
B
G I P J A
NOTE (1) Each lead centerline is located within 0.08 mm (0.003 inch) of its true position (T.P.) at maximum material condition. (2) "A" excludes mold flash. (Includes mold flash : 8.3 mm MAX. <0.331 inch MAX.>)
ITEM A B C D G H I J K L M N P Q R S T U
MILLIMETERS 8.00.1 0.45 MAX. 0.5 (T.P.) 0.220.05 1.00.05 12.40.2 11.80.1 0.80.2 0.145 +0.025 -0.015 0.5 0.08 0.08 13.40.2 0.10.05 3 +5 -3 1.2 MAX. 0.25 0.160.15
INCHES 0.3150.004 0.018 MAX. 0.02 (T.P.) 0.009 +0.002 -0.003 0.039 +0.003 -0.009 0.4880.008 0.465 +0.004 -0.005 0.031 +0.009 -0.008 0.0060.001 0.020 0.003 0.003 0.528 +0.008 -0.009 0.0040.002 3 +5 -3 0.048 MAX. 0.01 0.006 +0.007 -0.006 P32GU-50-9KH
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PD431000A-X
Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the PD431000A-X.
Types of Surface Mount Device
PD431000AGZ-X-KJH: 32-pin plastic TSOP(I) (8 x 20 mm) (Normal bent) PD431000AGZ-X-KKH: 32-pin plastic TSOP(I) (8 x 20 mm) (Reverse bent) PD431000AGU-X-9JH: 32-pin plastic TSOP(I) (8 x 13.4 mm) (Normal bent) PD431000AGU-X-9KH: 32-pin plastic TSOP(I) (8 x 13.4 mm) (Reverse bent)
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PD431000A-X
[MEMO]
25
PD431000A-X
[MEMO]
26
PD431000A-X
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
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PD431000A-X
[MEMO]
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product.
M4 96.5
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